Glossary entry

English term or phrase:

repeating mosaic

Chinese translation:

重复的图案

Added to glossary by clearwater
Jan 23, 2007 11:54
17 yrs ago
English term

repeating mosaic

English to Chinese Tech/Engineering IT (Information Technology) memory
But those advantages come at a cost. A 200-millimeter SOI wafer sells for about $275, while a plain silicon wafer of the same size goes for $65. Mark-Eric Jones, Innovative Silicon’s president and CEO, points out that as a percentage of total cost, the price gap collapses considerably once you factor in the $2400 in processing needed to turn a blank wafer of either substrate into a repeating mosaic of microchips. Still, all things being equal, the SOI chip will cost almost 9 ­percent more than the bulk-silicon chip.
这是指什么样的微芯片?
Proposed translations (Chinese)
2 +1 重复的图案
Change log

Jan 30, 2007 10:58: Jianjun Zhang changed "Level" from "Non-PRO" to "PRO"

Proposed translations

+1
3 hrs
Selected

重复的图案

好像mosaic在这里不一定是一个很技术的词

关于"Z"记忆芯片的摘要:
http://www.spectrum.ieee.org/print/4839
That’s why Innovative Silicon, which is essentially an intellectual property firm, may have the last laugh. The company, which is in Lausanne, has developed what it says is the densest—and cheapest—embedded memory technology in the world. It’s called Z-RAM, for zero-capacitor dynamic random access memory, and if it grabs even a little piece of the on-chip memory market, it will change the ground rules for microprocessor design and quickly make Innovative Silicon a company to be reckoned with.

An SOI wafer differs from an ordinary silicon wafer in that it has a very thin layer of insulating silicon dioxide buried a few hundred nanometers or less below the surface. That layer of insulation cuts the transistor off from the vast bulk of the wafer—which, in turn, limits the amount of charge the transistor must move in order to switch on or off.

But all things are no longer equal. The SOI wafer lets you substitute Z-RAM for the chip’s conventional embedded memory. SOI’s insulating layer is key to storing the bit in Z-RAM, so you cannot build it on a plain wafer. By Innovative Silicon’s estimates, if the conventional memory takes up half the area, replacing it with Z-RAM would let designers shrink a chip to 72 square milli­meters from 120 mm2. That would boost the number of chips per wafer and cut the final cost of the chip almost in half. Suddenly, SOI looks like a bargain.

Z-RAM eliminates the large, difficult-to-construct capacitor in a DRAM memory cell [top] by using a silicon substrate that has a layer of silicon dioxide insulation buried within it.


Peer comment(s):

agree Danbing HE
7 days
Thank you, Danbing.
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4 KudoZ points awarded for this answer. Comment: "谢谢!"
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